INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM FEATURES PIN NAMES Functional Description
The IM 1245Y–100 is a 1,048,576 bit, fully static
NP RAM organized as 128K X 8 using CMOS and an
This ‘NO POWER’ RAM has all the normal
characteristics of a CMOS static RAM with an impor-
tant benefit of data being retained in the absence of
power. Data retention current is so small that a minia-
ture lithium cell contained within the package providesan energy source to preserve data. Protection againstdata loss has also been incorporated to maintain dataintegrity during power on/off conditions.
The IM 1245Y–100 RAM can be directly used in placeof existing static RAMs. There is no limit to the numberof write cycles that can be executed and no additionalsupport circuitry is required for interface to a micropro-cessor.
INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com
INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM READ MODE Maximum Ratings
The IM 1245Y-100 performs a read cycle when-
ever WE high and CE low. The unique address speci-fied by the 17 address inputs A0-A16 defines which of
the 131,072 bytes of data is to be accessed. Valid data
will be available to the eight data output drivers withinaccess time t
And Time………………….260oC for 10 sec
provided that CE and OE access times are satisfied. If
OE or CE access times are not satisfied, data accesswill be measured from the limiting parameter (t or t ),
Input Voltage………………-0.5V to 7.0V
rather than address. The state of the eight data I/O
Input/ Output Voltage…….-0.5V to Vcc + 0.3V
lines is controlled by the OE and CE control signals. The data lines may be in an indeterminate state be-
WRITE MODE Recommended D.C. Operating Conditions
The IM 1245Y-100 is in the write mode whenever CEand WE inputs are held low. The latter occurring falling
edge of either CE or WE determines the start of a write
cycle. A write is terminated by the earlier rising edge of
CE or WE. The address must be held valid throughoutthe write cycle. WE must return to the high state for a
Write cycle can be initiated. CE or WE is high during
power on to perfect memory after Vcc reaches Vcc (min)but before the processor stabilizes. FRESHNESS SEAL AND SHIPPING DATA RETENTION
The IM1245Y - 100 is shipped from INNOVATIVEMICROTECHONOLOGY INC. with the lithium energy
The IM 1245Y-100 provides full functional ca-
source disconnected , guaranteeing full energy capac-
pability for Vcc greater than 4.5V and write protects at
ity. When Vcc is first applied at a level of greater than
4.25V. Data is retained in the absence of Vcc without
4.5 volts, the lithium energy source is enabled for bat-
any additional support circuitry. The SRAM constantly
monitors Vcc. The moment Vcc decays, the RAM au-tomatically write protects itself. All inputs to the RAMbecome “don’t care” and all outputs are in high imped-ance-state. As Vcc falls below approximately 3.0V thepower switching circuit connects the lithium energysource to RAM to retain data. During power-on, whenVcc rises above approximately 3.0V the power switch-ing circuit connects external Vcc to the RAM and dis-connects the lithium energy source. Normal RAM op-eration can resume after Vcc becomes greater than4.5V. INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM Electrical Characeteristics Parameter Description Test conditons Capacitance Parameter Description Test conditons INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM Switching Characteristics over the operating range Parameter Description INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM READ CYCLE WRITE CYCLE 1 INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM WRITE CYCLE 2 POWER – DOWN/ POWER –ON CONDITION
4.75V —————————————————————————————————————————————————
3.2V ——————————————————————————————————————————————————
During write cycle that is controlled by CE, output buffer is in high impedance state irrespective of whether OEis high or low level.
During write cycle that is controlled by WE, output buffer is in high impedance state if OE is high. INNOVATIVE IM1245Y-100 128K X 8 NO POWER SRAM DIM IN INCHES MIN.
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